1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, it relates to a data bus employed for transmitting data in a semiconductor memory device.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as DRAM) includes an EDO (extended data out) DRAM, which can consecutively read data at a high speed.
The EDO DRAM can read data at a higher speed than a general DRAM.
The general DRAM specifies a row address and a column address for reading data, and thereafter temporarily nullifies the column address when shifting to a subsequent address.
The EDO DRAM holds a column address and hence a memory controller specifying any column address can immediately nullify the column address. Thus, the speed of the system is increased since the column address may not be held until reading data.
FIGS. 28A and 28B illustrate the structure of data buses of a conventional EDO DRAM.
Referring to FIGS. 28A and 28B, this EDO DRAM has memory mats 504#1 to 504#4 arranged in two rows and two columns, each having a rectangular shape.
Each memory mat outputs 32 pairs of global I/O lines I/O0 to I/O31, which are connected to the data buses arranged on a central area provided between the memory mats along a shorter side of a chip.
Four data buses are provided for each memory mat along a shorter side of the memory mat, and these data buses are input in selectors 502#1 to 502#4 provided on central portions of the chip.
Outputs of the selectors 502#1 to 502#4 are connected to data buses drv0 to drv15 provided on an area between the memory mats along a longer side of the chip. The data buses drv0 to drv15 are connected to pads provided on an area between the memory mats 504#3 and 504#4.
FIG. 29 illustrates the correspondence between the data buses drv0 to drv15 shown in FIGS. 28A and 28B and data input/output terminals DQ0 to DQ15.
Referring to FIGS. 28A, 28B and 29, the conventional EDO DRAM can switch the bus width of output data to four bits, eight bits and 16 bits by controlling a mode selection signal.
The selectors 502#1 to 502#4 receive the mode selection signal for switching the bit width and parts of address signals, for selecting necessary data from the four data buses provided in correspondence to each memory mat in response to these control signals.
While the semiconductor memory device is tested with a tester and thereafter regarded as the final product, a multi I/O test is executed so that a plurality of semiconductor devices can be simultaneously tested with a tester having a small number of channels by reducing the number of terminals inputting/outputting data.
Also when executing this multi I/O test, control signals are transmitted to the selectors 502#1 to 502#4 so that four data terminals DQ0 to DQ3 can simultaneously supply data to the data buses provided along the shorter sides of all memory mats.
In this case, the data terminal DQ0 simultaneously supplies data to data buses 0, 4, 2 and 6 provided on the side of the memory mat 504#1, and the data terminal DQ3 simultaneously supplies data to data buses 9, 11, 13 and 15 provided on the side of the memory mat 504#4.
Further, the data terminal DQ1 simultaneously supplies data to data buses 1, 3, 5 and 7 provided on the side of the memory mat 504#1, and the data terminal DQ2 simultaneously supplies data to data buses 8, 10, 12 and 14 provided on the side of the memory mat 504#3.
FIG. 30 is a schematic diagram for illustrating the arrangement of data buses for each mat in the conventional EDO DRAM.
Referring to FIG. 30, data terminals 513 are provided on a central area along the longer side of the chip, and a row and column address buffer 524 is provided at the center of the chip.
The row and column address buffer 524 receives externally supplied address signals A0 to A12, captures addresses and partially decodes the same in response to a control signal /CAS, and outputs signals Y less than 15:0 greater than  and CAD8 to a predecoder zone 554#3.
Data externally supplied to the data terminals 513 reach a selector 502#3 via input buffers 520. The selector 502#3 is supplied with mode selection signals B8E and B16E switching the bit width of the data, and outputs data to write data buses located between the predecoder zone 554#3 and a preamplifier+write driver zone 562#3.
The data output to the write data buses reach write drivers included in the preamplifier+write driver zone 562#3, and the write drivers output the data to the global I/O lines I/O0 to I/O31.
The predecoder zone 554#3 outputs a predecoded address signal YA-YC toward a column decoder 528#3. The column decoder 528#3 responsively selects a corresponding column of a 16-megabit memory mat 504#3 for writing the data therein.
In data reading, data read onto the pairs of global I/O lines I/O0 to I/O 31 from a column selected by the column decoder 528#3 reach preamplifiers included in the preamplifier+write driver zone 562#3, and the preamplifiers output the data to read data buses provided between the predecoder zone 554#3 and the preamplifier+write driver zone 562#3.
The data read on the read data buses are input in the selector 502#3, which in turn selects and outputs the data in response to the mode selection signals B8E and B16E.
The data output from the selector 502#3 reach the data terminals 513 via data output buffers 534. Then the data are read out from the data terminals 513.
In the conventional structure of the data buses, the outputs from the preamplifiers reach the data terminals 513 through the selector 502#3. In other words, bus transfer is performed.
In the selector 502#3, data paths vary with the selected modes and hence critical timing adjustment is necessary. However, such timing adjustment is hard to attain.
FIG. 31 is a diagram for illustrating a multi-bit test in the conventional EDO DRAM.
Referring to FIG. 31, each pair of local I/O lines provided along the shorter side of each mat is divided into four in general. Two modes are employed for the multi-bit test.
In the first mode, a single word line WL and four column selection lines CSL are activated for each mat. Each column selection line outputs 4-bit data, and hence each mat outputs 16-bit data. The 16-bit data is degenerated by wired ORing on a pair of read data lines. Data of 16xc3x974=64 bits are degenerated in the four mats in total.
In the second mode, two word lines WL and four column selection lines CSL are activated for each mat. Thus, each column selection line outputs 8-bit data, and hence each mat outputs 32-bit data. The 32-bit data is degenerated by wired ORing on a pair of read data lines. Data of 32xc3x974=128 bits are degenerated in the four mats in total.
Thus, each mat requires 32 preamplifiers and 32 write drivers accompanying the pairs of global I/O lines.
FIG. 32 is a diagram for illustrating the arrangement of equalizer circuits LEQ for equalizing pairs of local I/O lines of the conventional EDO DRAM and equalizer signals activating the equalizer circuits LEQ.
Referring to FIG. 32, each pair of local I/O lines is divided into four along the shorter side of the memory mat 504#3 and the equalizer circuits LEQ are discretely arranged along the shorter side of the chip, and hence a number of control signal lines are necessary for transmitting control signals LIOEQ less than 0 greater than  to LIOEQ less than 16 greater than  for activating the equalizer circuits LEQ. Thus, the degree of freedom in arrangement of the pairs of global I/O lines is disadvantageously insufficient.
An object of the present invention is to provide a semiconductor memory device having simple data buses requiring no complicated timing adjustment and capable of reducing the accompanying circuit scale.
Briefly stated, the present invention provides a semiconductor memory device capable of switching the number of terminals inputting/outputting data from/to an external device with a mode switching signal, which comprises a plurality of memory mats, a plurality of data buses and a plurality of input/output circuit zones.
Each of the plurality of memory mats has a rectangular shape. Each memory mat includes a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines provided in correspondence to the columns of the plurality of memory cells, and a plurality of pairs of global I/O lines transmitting/receiving data to/from the plurality of pairs of bit lines.
The plurality of data buses are provided in correspondence to each memory mat, and at least partially arranged in parallel with a shorter side of each memory mat. The plurality of input/output circuit zones are provided along the shorter side of each memory mat, and transfer data between the plurality of pairs of global I/O lines and the data buses.
Each input/output circuit zone includes a selection portion selecting data lines corresponding to the plurality of pairs of global I/O lines respectively from a plurality of data lines included in the data buses in response to the mode switching signal.
According to another aspect of the present invention, a semiconductor memory device has first and second multi-bit test modes capable of simultaneously writing test data supplied to a single data input/output pad in a plurality of memory cells, and comprises a memory mat and an input/output circuit zone.
The memory mat includes a plurality of memory cells arranged in rows and columns. The memory mat further includes a first pair of bit lines, provided in correspondence to first column of the memory cells, including first and second bit lines transmitting complementary signals, a second pair of bit lines, provided in correspondence to second column of the memory cells, including a third bit line adjacent to the second bit line and a fourth bit line transmitting complementary signals with the third bit line, a first pair of data lines transmitting data to the first pair of bit lines and a second pair of data lines transmitting data to the second pair of bit lines.
The input/output circuit zone inputs/outputs data in/from the memory mat. The input/output circuit zone includes a first transmission circuit transmitting data supplied to a data input/output pad to the first pair of data lines in first and second multi-bit test modes and a second transmission circuit transmitting the data supplied to the data input/output pad to the second pair of data lines with reverse polarity in the first multi-bit test mode and with straight polarity in the second multi-bit test mode.
Therefore, a principal advantage of the present invention resides in that no complicated timing adjustment is necessary and hence the semiconductor memory device is easy to design and the accompanying circuit scale can be reduced.
Another advantage of the present invention resides in that short-circuiting across alternate bit lines can be detected in a multi-bit test.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.